In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials can be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates, such as semiconductor wafers. In conventional CMP, a wafer is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a polishing composition (“slurry”) or other polishing solution is provided between the wafer and the polishing pad. Thus, the wafer surface is polished and made planar by the chemical and mechanical action of the pad surface and slurry.
Certain advanced device designs demand polishing compositions that provide enhanced silicon oxide removal efficiency at lower point-of-use (POU) abrasive wt % as well as reduced scratch defects for the improvement of polishing processes throughout and product yield %. As the size of structures on semiconductors devices continue to shrink, performance criteria which was once acceptable for planarizing and reducing defects of polishing dielectric materials becomes increasingly less acceptable. Scratches which were once considered acceptable are today becoming yield limiting.
Accordingly, there is a need for polishing compositions and polishing methods that exhibit desirable planarization efficiency, uniformity, and dielectric removal rate while minimizing defects such as scratches.